syntax in assignment statement l value verilog

Verilog assign statement

Hardware schematic.

Signals of type wire or a similar wire like data type requires the continuous assignment of a value. For example, consider an electrical wire used to connect pieces on a breadboard. As long as the +5V battery is applied to one end of the wire, the component connected to the other end of the wire will get the required voltage.

In Verilog, this concept is realized by the assign statement where any wire or other similar wire like data-types can be driven continuously with a value. The value can either be a constant or an expression comprising of a group of signals.

Assign Syntax

The assignment syntax starts with the keyword assign followed by the signal name which can be either a single signal or a concatenation of different signal nets. The drive strength and delay are optional and are mostly used for dataflow modeling than synthesizing into real hardware. The expression or signal on the right hand side is evaluated and assigned to the net or expression of nets on the left hand side.

Delay values are useful for specifying delays for gates and are used to model timing behavior in real hardware because the value dictates when the net should be assigned with the evaluated value.

• LHS should always be a scalar or vector net or a concatenation of scalar or vector nets and never a scalar or vector register.
• RHS can contain scalar or vector registers and function calls.
• Whenever any operand on the RHS changes in value, LHS will be updated with the new value.
• assign statements are also called continuous assignments and are always active

In the following example, a net called out is driven continuously by an expression of signals. i1 and i2 with the logical AND & form the expression.

If the wires are instead converted into ports and synthesized, we will get an RTL schematic like the one shown below after synthesis.

Continuous assignment statement can be used to represent combinational gates in Verilog.

The module shown below takes two inputs and uses an assign statement to drive the output z using part-select and multiple bit concatenations. Treat each case as the only code in the module, else many assign statements on the same signal will definitely make the output become X.

Assign reg variables

It is illegal to drive or assign reg type variables with an assign statement. This is because a reg variable is capable of storing data and does not require to be driven continuously. reg signals can only be driven in procedural blocks like initial and always .

Implicit Continuous Assignment

When an assign statement is used to assign the given net with some value, it is called explicit assignment. Verilog also allows an assignment to be done when the net is declared and is called implicit assignment.

Combinational Logic Design

Consider the following digital circuit made from combinational gates and the corresponding Verilog code.

Combinational logic requires the inputs to be continuously driven to maintain the output unlike sequential elements like flip flops where the value is captured and stored at the edge of a clock. So an assign statement fits the purpose the well because the output o is updated whenever any of the inputs on the right hand side change.

After design elaboration and synthesis, we do get to see a combinational circuit that would behave the same way as modeled by the assign statement.

See that the signal o becomes 1 whenever the combinational expression on the RHS becomes true. Similarly o becomes 0 when RHS is false. Output o is X from 0ns to 10ns because inputs are X during the same time.

Click here for a slideshow with simulation example !

• The Verilog-AMS Language
• Analog Processes
• Assignment Statements

Assignment Statements 

Contribution .

A contribution statement is used to give values to continuous signals, in particular to branch potentials or flows:

This statement says that the voltage on the branch named ‘res’ should be driven so that the voltage on the branch should equal r multiplied by the current through the branch.

Contributions may be either explicit, as above, or implicit. Implicit contributions have the target on both sides of the contribution operator. For example:

This implements the series combination of a resistor and a capacitor.

Implicit contributions to branch flows can be used to easily create series combinations whereas implicit contributions to branch potentials can be used to create parallel combinations. For example, the following creates the parallel combination of an inductor and a conductor:

Multiple contributions to the same branch in the same analog process accumulate. For example:

This is equivalent to:

Multiple contributions to a branch flow can be viewed as creating multiple parallel branches. For example, the above example is equivalent to the parallel combination of the output of a controlled current source, a conductor, and a capacitor. Similarly, multiple contributions to a branch potential can be viewed as creating multiple series branches.

The target (left side) must be a branch signal: an access function applied to a continuous branch. The branch may be a named (or explicit) branch, or it may be an unnamed (or implicit) branch, which are given as a single net or a pair of nets. When an implicit branch is given as a pair of nets, the branch is assumed to connect the two nets. When an implicit branch is specified as a single net, the branch is assumed to connect that net to ground.

Here is a resistor module that uses a explicitly declared or named branch:

Here is a resistor module that uses a implicitly declared or unnamed branch:

Descriptions that employ unnamed branches are a little more compact, but also the formulation of the branches is constrained (multiple contributions to flows give a shunt toplogy and to potentials gives a series topology). For this reason people use unnamed branches with the branch topology is simple, and switch to named branches for the more complicated topologies.

The actual contributions occur after the analog block has been evaluated, meaning that the branch values do not change between statements in the analog block. As such, so as long as the values of the right-hand side expressions are not affected, the order of the contribution statements is inconsequential. So for example, these two analog blocks are equivalent:

Indirect Assignment 

An indirect assignment is an alternative to the contribution statement. It also drives a particular branch potential or flow so that a given equation is satisfied, but in this case the driven branch potential or flow need not be in the specified equation. This feature is rarely needed, however it occasionally allows you to describe a component that would cumbersome to describe with contributions. For example, it is possible to describe an ideal opamp using:

This can be read as ‘drive V(out) such that V(pin,nin) == 0’.

The left side of the equation must be either a branch potential or flow, the right side is an expression. The equation may be implicit or explicit.

The driven branch must not also be a target of a contribution statement.

Assignment 

A assignment evaluates the expression on its right hand side and then immediately assigns the value to the variable on its left hand side:

The target (left side) of an analog assignment statement may only be a integer or real variable. It may not be signal or a wire.

Contribution versus Assignment 

For people new to Verilog-A and Verilog-AMS, contribution and assignment seem to be doing very similar things, and this can confuse them. Here the differences between contribution and assignment are highlighted.

问 错误:赋值语句中的语法l-value EN

这是Verilog代码。

我得到了以下错误。你能帮我了解如何修复它们吗？

Stack Overflow用户

发布于 2020-12-20 19:35:17

您的代码中有一些语法错误。

不要使用 assign 关键字为 reg ( F1 )赋值。

不要将模块实例( sub )放在 always 块中。

使用 sub 模块实例的实例名称。

请勿创建与模块( sub )同名的 task 。在这种情况下，不需要 task/endtask 。

这是一个为我干净利落地编译的版本：

https://stackoverflow.com/questions/65377518

Copyright © 2013 - 2024 Tencent Cloud. All Rights Reserved. 腾讯云 版权所有 

深圳市腾讯计算机系统有限公司 ICP备案/许可证号： 粤B2-20090059  深公网安备号 44030502008569

腾讯云计算（北京）有限责任公司 京ICP证150476号 |   京ICP备11018762号 | 京公网安备号11010802020287

Assign Statement In Verilog

• You can use assign statement inside of module.
• You can use assign statement to output port and any wire declared inside the module

Examples of assign statement

In above example, y is output port and we are assigning this output port to a and b. It will create a and gate where a and b are inputs and y is output

In above example, we've descrived a NAND gate. We can use one statemetn but for better understanding we've use two statement to illustrate how we can use assign statement to both wire and output port. wire w is assign with a AND b, and output y is assigned not of wire w. This creates a NAND gate in verilog HDL.

In above example, we have described a full-adder using assign statement. Note that we can write complete boolean equation using assign statement

We can also use Verilog operators using assign statement. Below is the example of full-adder using assign statement and Verilog operator

In above example, we are using + operator, which addition operator in Verilog. We are assigning output sum and carry with addition of a, b and cin.

Click like if you found this useful

Add Comment

This policy contains information about your privacy. By posting, you are declaring that you understand this policy:

• Your name, rating, website address, town, country, state and comment will be publicly displayed if entered.
• Your IP address (not displayed)
• The time/date of your submission (displayed)
• Administrative purposes, should a need to contact you arise.
• To inform you of new comments, should you subscribe to receive notifications.
• A cookie may be set on your computer. This is used to remember your inputs. It will expire by itself.

This policy is subject to change at any time and without notice.

These terms and conditions contain rules about posting comments. By submitting a comment, you are declaring that you agree with these rules:

• Although the administrator will attempt to moderate comments, it is impossible for every comment to have been moderated at any given time.
• You acknowledge that all comments express the views and opinions of the original author and not those of the administrator.
• You agree not to post any material which is knowingly false, obscene, hateful, threatening, harassing or invasive of a person's privacy.
• The administrator has the right to edit, move or remove any comment for any reason and without notice.

Failure to comply with these rules may result in being banned from submitting further comments.

These terms and conditions are subject to change at any time and without notice.

A continuous assignment drives a value into a net.

Description:

Continuous assignments model combinational logic. Each time the expression changes on the right-hand side, the right-hand side is re-evaluated, and the result is assigned to the net on the left-hand side.

The implicit continuous assignment combines the net declaration (see Net data type) and continuous assignment into one statement. The explicit assignment require two statements: one to declare the net (see Net data type), and one to continuously assign a value to it.

Continuous assignments are not the same as procedural continuous assignments. Continuous assignments are declared outside of procedural blocks. They automatically become active at time zero, and are evaluated concurrently with procedural blocks, module instances, and primitive instances.

Net data type , Procedural continuous assignment

Procedural Assignments

In the dataflow modeling, a continuous assignment statement is discussed where LHS expression is always updated for changes in RHS expression. Refer to c ontinuous assignment for more details. In the case of procedural assignment, the LHS variable remains unchanged until the same value is updated by the next procedural statement.

• RHS expression can be a value or an expression that evaluates to a value.
• LHS expression can be reg, integer, real, time-variable, or memory element.
• The procedural assignments can be placed inside procedural blocks like initial and always blocks. They can also be placed inside tasks and functions. 
• The procedural assignments can also be placed directly inside a module while declaring a variable. (Ex. reg [3:0] i_data = 4’h7)

There are two types of procedural assignments and both of them are widely used in the designs written in the Verilog language.

• Blocking assignments
• Non-blocking assignments

Blocking Assignments

The blocking assignment statements are executed sequentially by evaluating the RHS operand and finishes the assignment to LHS operand without any interruption from another Verilog statement. Hence, it blocks other assignments until the current assignment completes and is named as “blocking assignment”. 

An equal ‘=’ is used as a symbol for the blocking assignment operator.

A blocking assignment does not block the execution of a statement in another procedural block. For example, two initial blocks start execution at the same simulation time. A blocking assignment in the first initial block does not block execution in another initial block.

Race around condition: A problem with blocking assignment

If a variable is used in LHS of blocking assignment in one procedural block and the same variable is used in RHS of another blocking assignment in another procedural block. The race-around condition can occur as an order of execution is unknown if both statements are scheduled at the same simulation time.

In this example, 

Since procedural blocks (both initial and always) can be executed in any order.

A. If the first initial block executed before the second initial block then 

• The value of y will be updated as 4‘h5 in the first initial block
• The value of data will be updated as 4‘h5 in the second initial block

B. If the second initial block executed before the first initial block then 

• The value of data will be updated as 4‘h3 in the second initial block
• The value of y will be updated as 4‘h3 in the first initial block

Verilog Tutorials

• Interview Q

Verilog Tutorial

• Send your Feedback to [email protected]

Help Others, Please Share

Learn Latest Tutorials

Transact-SQL

Reinforcement Learning

R Programming

React Native

Python Design Patterns

Python Pillow

Python Turtle

Preparation

Verbal Ability

Interview Questions

Company Questions

Trending Technologies

Artificial Intelligence

Cloud Computing

Data Science

Machine Learning

B.Tech / MCA

Data Structures

Operating System

Computer Network

Compiler Design

Computer Organization

Discrete Mathematics

Ethical Hacking

Computer Graphics

Software Engineering

Web Technology

Cyber Security

C Programming

Control System

Data Mining

Data Warehouse

Error: Syntax in assignment statement l-value

This is the Verilog code.

I'm getting the following errors. Can you help me understand how to fix them?

solution1  0  2020-12-20 11:35:16

There are a few syntax errors with your code.

Do not use the assign keyword to make an assignment to a reg ( F1 ). assign 关键字对 reg ( F1 ) 进行赋值。-->

Do not place a module instance ( sub ) inside an always block. sub ) 放在 always 块内。-->

Use an instance name for your sub module instance. sub 模块实例使用实例名称。-->

Do not create a task with the same name as a module ( sub ). sub ) 同名的 task 。--> There is no need for the task/endtask in this case. task/endtask 。-->

Here is a version which compiles cleanly for me:

• Related Question
• Related Blog
• Related Tutorials

The technical post webpages of this site follow the CC BY-SA 4.0 protocol. If you need to reprint, please indicate the site URL or the original address.Any question please contact:[email protected].

• system-verilog
• digital-logic
• syntax-error
• digital-design