vivado 报错之procedural assignment to a non-register result is not permitted“
这个错误通常是由于尝试在非寄存器类型的对象上进行过程赋值所引起的。在 Verilog 中，当使用 always 块时，其中的赋值操作应该只用于寄存器类型的变量，比如 reg 类型。非寄存器类型的信号（比如 wire ）不能在 always 块内进行赋值。
出现这个错误的原因可能是在非寄存器类型的信号上尝试进行赋值操作。在您的代码中，如果 output_data 是一个 wire 类型的信号，而您尝试在 always 块内给它赋值，这将导致这个错误。
解决这个问题的方法是将 output_data 声明为 reg 类型，而不是 wire 类型。修改代码如下：
通过将 output_data 的声明从 wire 改为 reg 类型，您可以在 always 块内对其进行赋值，从而避免这个错误。
“相关推荐”对你有帮助么？
请填写红包祝福语或标题
1.余额是钱包充值的虚拟货币，按照1:1的比例进行支付金额的抵扣。 2.余额无法直接购买下载，可以购买VIP、付费专栏及课程。
tapajitm (Member) asked a question.
- Simulation & Verification
hemangd (AMD)
Admin Note – This thread was edited to update links as a result of our community migration. The original post date was 2020-05-02.
baltintop (Member)
- CORDIC sin_cos ( CLK_100MHZ , angle , Xin , Yin , Xout , Yout );
tapajitm (Member)
Related Questions
Community Feedback?
Verilog: Continuous & Procedural Assignments
Continuous Assignment
Continuous assignment is used to drive a value on to a net in dataflow modeling. The net can be a vector or scalar, indexed part select, constant bit or part select of a vector. Concatenation is also supported with scalar vector types.
module Conti_Assignment (addr1,addr2,wr,din,valid1,valid2,dout); input [31:0] addr1,addr2; input [31:0] din; output [31:0] dout; input valid1,valid2,wr;
wire valid; wire [31:0] addr;
//Net (scalar) continuous assignment assign valid = valid1 | valid2;
//Vector continuous assignment assign addr[31:0] = addr1[31:0] ^ addr2[31:0];
//Part select & Concatenation in Continuous assignment assign dout[31:0] = (valid & wr) ? {din[31:2],2'b11} : 32'd0;
Regular & Implicit Assignment
Regular continuous assignment means, the declaration of a net and its continuous assignments are done in two different statements. But in implicit assignment, continuous assignment can be done on a net when it is declared itself. In the below example, `valid` is declared as wire during the assignment. If signal name is used to the left of the continuous assignment, an implicit net declaration will be inferred. In the below code `dout` is not declared as net, but it is inferred during assignment.
module Implicit_Conti_Assignment (addr1,addr2,wr,din,valid1,valid2,dout); input [31:0] addr1,addr2; input [31:0] din; output [31:0] dout; input valid1,valid2,wr;
//Net (scalar) Implict continuous assignment wire valid = (valid1 | valid2);
//Implicit net declaration -dout assign dout[31:0] = (valid & wr) ? {din[31:2],2'b11} : 32'd0;
Procedural Assignment
We have already seen that continuous assignment updates net, but procedural assignment update values of reg, real, integer or time variable. The constant part select, indexed part select and bit select are possible for vector reg.
There are two types of procedural assignments called blocking and non-blocking. Blocking assignment, as the name says, gets executed in the order statements are specified. The "=" is the symbol used for blocking assignment representation. Non-blocking assignment allows scheduling of assignments. It will not block the execution. The symbol "<=" is used for non-blocking assignment representation and mainly used for concurrent data transfers.
Following example shows the differences in the simulation result by using blocking and non-blocking assignments.
/* module Nonblocking_Assignment (addr1,addr2,wr,din,valid1,valid2,data,aout); input [31:0] addr1,addr2; input [31:0] din; output [31:0] data,aout; input valid1,valid2,wr;
reg [31:0] data,aout, addr; reg valid;
always @(addr1,addr2,wr,din,valid1,valid2) begin valid <= (valid1 | valid2); addr <= (addr1[31:0] | addr2[31:0]); data <= (valid & wr) ? {din[31:2],2'b11} : 32'd0; aout <= wr ? addr: {addr1[15:0],addr2[31:16]}; end initial $monitor($time,"NON-BLOCKING: Values valid1=%b, valid2=%b, wr=%b, addr1=%d, addr2=%d, data=%d, aout=%d", valid1,valid2,wr,addr1,addr2,data,aout); endmodule */ module Blocking_Assignment (addr1,addr2,wr,din,valid1,valid2,data,aout); input [31:0] addr1,addr2; input [31:0] din; output [31:0] data,aout; input valid1,valid2,wr;
always @(addr1,addr2,wr,din,valid1,valid2) begin valid = (valid1 | valid2); addr = (addr1[31:0] | addr2[31:0]); data = (valid & wr) ? {din[31:2],2'b11} : 32'd0; aout = wr ? addr : {addr1[15:0],addr2[31:16]}; $monitor($time,"BLOCKING: Values valid1=%b, valid2=%b, wr=%b, addr1=%d, addr2=%d, data=%d, aout=%d", valid1,valid2,wr,addr1,addr2,data,aout); end endmodule
module test; reg valid1,valid2,wr; reg [31:0] addr1,addr2,din; wire [31:0] data,aout;
Blocking_Assignment Block_Assign(addr1,addr2,wr,din,valid1,valid2,data,aout);
//Nonblocking_Assignment Nonblock_Assign(addr1,addr2,wr,din,valid1,valid2,data,aout);
initial begin valid1 = 0; valid2 = 0; addr1 = 32'd12; addr2 = 32'd36; din = 32'd198; wr = 1;
#5 valid1 = 1; #10 valid1 = 0; valid2 = 1; #10 addr1 = 32'd0; addr2 = 32'd0; #5 wr = 0; #12 wr = 1;
/* ncsim> run 0NON-BLOCKING: Values valid1=0, valid2=0, wr=1, addr1= 12, addr2= 36, data= X, aout= x 5NON-BLOCKING: Values valid1=1, valid2=0, wr=1, addr1= 12, addr2= 36, data= 0, aout= 44 15NON-BLOCKING: Values valid1=0, valid2=1, wr=1, addr1= 12, addr2= 36, data= 199, aout= 44 25NON-BLOCKING: Values valid1=0, valid2=1, wr=1, addr1= 0, addr2= 0, data= 199, aout= 44 30NON-BLOCKING: Values valid1=0, valid2=1, wr=0, addr1= 0, addr2= 0, data= 0, aout= 0 42NON-BLOCKING: Values valid1=0, valid2=1, wr=1, addr1= 0, addr2= 0, data= 199, aout= 0 ncsim: *W,RNQUIE: Simulation is complete. */
/* ncsim> run 0BLOCKING: Values valid1=0, valid2=0, wr=1, addr1= 12, addr2= 36, data= 0, aout= 44 5BLOCKING: Values valid1=1, valid2=0, wr=1, addr1= 12, addr2= 36, data= 199, aout= 44 15BLOCKING: Values valid1=0, valid2=1, wr=1, addr1= 12, addr2= 36, data= 199, aout= 44 25BLOCKING: Values valid1=0, valid2=1, wr=1, addr1= 0, addr2= 0, data= 199, aout= 0 30BLOCKING: Values valid1=0, valid2=1, wr=0, addr1= 0, addr2= 0, data= 0, aout= 0 42BLOCKING: Values valid1=0, valid2=1, wr=1, addr1= 0, addr2= 0, data= 199, aout= 0 ncsim: *W,RNQUIE: Simulation is complete. ncsim> exit */
IMAGES
VIDEO
COMMENTS
Note: IEEE is considering depreciating procedural continuous assignment, so in the future it will likely become illegal syntax. IEEE Std 1800-2012 C.4.2 Procedural assign and deassign statements : The procedural assign and deassign statements can be a source of design errors and can be an impediment to tool implementation.
The LHS of an assignment in a procedural block must be of type reg.Procedural assignment statements assign values to reg, integer, real, or time variables and can not assign values to wire.Note that reg can hold or store some value depending on some triggering event, while wire cannot store any value.. Here, k is holding some value till the addr signal changes.
Variables are driven by procedural assignments. In SystemVerilog: Nets are driven by any number of continuous assigns or ports - conflict resolution determines the final value if multiple drivers exists. Variables are driven by procedural assignments or a single continuous assign or port (not both) - since there is only one continuous assign ...
Tour Start here for a quick overview of the site Help Center Detailed answers to any questions you might have Meta Discuss the workings and policies of this site
(VERI-1100) procedural assignment to a non-register 'nextstate' is not permitted. The problem is mostly with the case statement. I am genuinely confused. My design clearly cannot be implemented using clocked registers for these signals. I've tried several versions, with assign, with and without always and can't get it to compile.
ERROR: [Synth 8-2577] procedural assignment to a non-register some_signal is not permitted, left-hand side should be reg / integer / time / genvar; Why do I need to define some_signal as a reg type? Thank you in advance for your responses and time! -anm
Looks like you have you direction reversed for the rx_data and tx_data parallel ports of the SPI module. Generally speaking, parallel rx_data should be the output of the SPI interface module, i.e. received data from the serial wires of the interface gets parallelized in the module, and then output to the rest of the FPGA.
tempreg is storing values and will not be purely combinational logic. Use the template below, and use non-blocking assignments to tempreg. If you don't use the clock, then you will have complex latching logic. If you don't use non-blocking, then there is a potential race condition in the Verilog simulator.
assign sw=LED; Something about this probably. Try doing sw <= LED; instead. The assign statement lives outside of your always blocks. Within those you want to only use nonblocking (<=) or blocking (=) operators. edit: What exactly are you trying to do? Where you're trying to assign sw to LED you're assigning an output to an input.
vivado报错：procedural assignment to a non-register result is not permitted" dcbjz: assign内被赋值的不应该是wire吗？ system generator结合高版本matlab的使用. CSDNLVCDWZQ: vivado或者vitis 2023的ml文件在哪，检索没有这个文件，相应的文件夹下也没有. vivado电路综合后模块消失
In general be cautious about mixing blocking and non-blocking assignments, what you have is fine, but it can be a bit more confusing to read which can lead to bugs being introduced if someone modifies it later. I would recommend adding comments saying something like: "temp signal for internal (to this block use only) using blocking assignments".
In response to your comment, there are non-procedural ways of doing things which do not require registers - any combinational circuit can be defined without the need for procedural blocks. An example in your case would be to use the ternary operator with a continuous assignment statement: assign O = SEL ? (A - B) : (A + B);
1.procedural assignment to a non-register DATA_BUS is not permitted 这种报错一般是在always语句中使用了非reg变量，在always语句中所有信号必须是reg变量，低级错误，（语法不熟悉） 2 出现的错误如下： ERROR:Xst:880 - "mst_pulse_calculation.v" line ...
I replaced CLK_100MHZ by clk_100MHZ but Now I am getting following errors.
Yes, they are equivalent. IEEE Std 1364-2005, section 6.2 Procedural assignments states:...procedural assignments put values in variables. The assignment does not have duration; instead, the variable holds the value of the assignment until the next procedural assignment to that variable. You do not need to use the 2nd code example.
There are two types of procedural assignments called blocking and non-blocking. Blocking assignment, as the name says, gets executed in the order statements are specified. The "=" is the symbol used for blocking assignment representation. Non-blocking assignment allows scheduling of assignments. It will not block the execution.
However a wire cannot be assigned in a procedural code (ex always block). So you need to think how to assign some bits to from a module and other from procedural. \$\endgroup\$ - Greg
The trailing comma in a port list is illegal. Change: output wire c, to: output wire c. It is illegal to assign a value to an input port inside a module. This is illegal: a=1'b1. Assuming it was a typo to use a there, and you really meant to type c, you should change: assign c=(a>b)?(a=1'b1):(c=1'b0);